In current HSPA and LTE modems the size of memory compared to the processing logic of L1 HW accelerators is roughly 1:1.5 (‘1 to 1.5’). As data rates increase in future, the size of memory will increase correspondingly, whilst the L1 HW may often be used (almost) as it is by increasing the clock rate of the processing logic. For example, in LTE-A, more carriers (for example 2-4 carriers) will be aggregated to the system and the size of the memory will increase correspondingly. However, it is possible to increase the clock frequency of the processing logic and thus time-share the existing HW accelerators and thus support LTE-A with minimum changes to the processing logic.
Optimizing the processing logic is possible but requires time and resources and typically provides only marginal gains. However, if the memory requirements can be lowered, significant chip area savings may be obtained with relatively small effort compared to processing logic optimization.
A paper by Wolfgang Rave, published in IEEE Signal Processing Letters, April 2009, entitled “Quantization of Log-Likelihood Ratios to Maximize Mutual Information” describes compression of Log-Likelihood Ratios.
A paper by Matteo Danieli et al, published in the 2010 IEEE Data Compression Conference, entitled “Maximum Mutual Information Vector Quantization of Log-Likelihood Ratios for Memory Efficient HARQ Implementations” describes the compression of HARQ data using Log-Likelihood Ratios.
It would therefore be desirable to provide improved ways of reducing memory requirements in modems.